The 25th International Conference on Amorphous and Nano-crystalline Semiconductors
August 18–23, 2013 Toronto, Ontario Canada
Nano- and Microcrystalline Silicon: Growth and Characterization IV
Chair: Zahangir Kabir, Concodia University
Preparation and Testing of the Silicon Nanowires
1. Institute of Physics, v. v. i., Academy of Sciences of the Czech Republic, Cukrovarnická 10, 162 00 Prague 6, Czech Republic
2. Physics Department, Faculty of Science, Tanta University, Tanta, 31527, Egypt
Growth of silicon nanowires (SiNWs) has attracted tremendous attention over the last decade due to their potential applications. SiNWs have been used as the basic building block in field effect transistors, single nanowire radial solar cells and molecular or biological sensors. Nanowires offer excellent light trapping, which could help to improve the efficiency of solar cells, similar to "black silicon"  or other approaches to nanometre scale structuring of the Si surfaces.
Growth of SiNWs has been demonstrated by so called VLS (Vapor Liquid Solid) method , using different metal catalysts, from which gold is often used because of the low eutectic temperature of Si-Au system (363°C). When monocrystalline silicon (mc-Si) is used as a substrate or starting material the regular SiNW arrays have been prepared by etching or growth . However, in this case usually rather high temperatures and/or expensive materials (mc-Si) are used.
Real challenge is to grow SiNWs at low temperatures on low-cost substrates. Plasma Enhanced Chemical Vapour Deposition (PECVD) is one of the techniques that can be used for this purpose . Recently it was used (with Sn as a catalyst) for instance for the SiNW solar cells .
We have demonstrated PECVD growth of ultrasharp (<10 nm) Si "nanoneedles" on glass at temperatures as low as 250°C [6,7]. The very specific feature of these nanoneedles is a very high ("explosive") growth-rate (15 nm/s). This complicates the growth of SiNW regular arrays but could be the advantage for preparation of the "lateral SiNWs".
In this paper we present detail study how to prepare and electrically characterize different forms of the lateral SiNWs on glass. We don't focus on characterization of standalone SiNW but rather on more application relevant electrode arrays with directed SiNW growth. Microscopic Ti contacts with the different gap spacing (0.5–4 μm) and 50 nm stripes of 3 nm thin Au between them are formed by lithographic techniques. The Au film is self-organized into a set of Au catalytic nanodots (size around 10 nm) by thermal annealing at temperature 400°C. SiNWs are then formed and localized between the Ti electrode tips by the PECVD process at the same temperature. The crystallinity of the SiNWs has been proved by micro-Raman spectroscopy and in addition basic electronic transport properties are studied. All these results together with the growth mechanism are discussed and future research directions indicated.
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Keywords: Si nanowires (SiNWs), growth of SiNWs, characterization by Raman and transport measurement
High-Performance Heterojunction Devices Enabled by Low-Temperature PECVD of Hydrogenated Crystalline and Amorphous Silicon
IBM T. J. Watson Research Center, Yorktown Heights, NY 10598
High-performance heterojunction devices enabled by plasma-enhanced chemical vapor deposition (PECVD) of epitaxially grown hydrogenated crystalline silicon (c-Si:H) and hydrogenated amorphous silicon (a-Si:H) layers grown in a same PECVD reactor at temperatures close to 200°C will be discussed. The impact of amorphous-to-crystalline and crystalline-to-amorphous phase transitions during the PECVD growth of the hydrogenated Si layers on the device performance will be highlighted. High-performance devices have been found to require epitaxial layers thinner than the diffusion length of minority carriers in the epitaxial layer. In particular, heterojunction solar cells with conversion efficiencies exceeding 21% on p-type and n-type crystalline Si substrates, and heterojunction bipolar transistors with current gains exceeding 500 on p-type c-Si substrates have been demonstrated. Application to heterojunction solar cells on crystalline germanium substrates and heterojunction field-effect transistors on crystalline Si substrates will be also discussed.
The authors are grateful to Dr. Devendra K. Sadana, Dr. Ghavam G. Shahidi and Dr. T-C. Chen of IBM Research for technical discussion and managerial support, and Prof. Sigurd Wagner of Princeton Univ. for allowing the usage of his PECVD facility for this work.
Keywords: amorphous silicon, PECVD, heterojunction solar cells, heterojunction transistors
Fabrication of High Gauge Factor Piezoresistive Nanocrystalline Si Film using Aluminum Induced Crystallization of HWCVD Deposited a-Si:H
1. Department of Metallurgical Engineering and Materials Science, IIT Bombay, Mumbai, India
2. Taiwan Semiconductor Manufacturing Company, Taiwan
3. Department of Metallurgical Engineering and Materials Science, IIT Bombay, Mumbai, India
Aluminum induced crystallization (AIC) has shown promising results towards achieving device quality nanocrystalline silicon (nc-Si) at lower temperature with the scope for large area deposition in contrast to solid phase crystallization (SPC) and laser induced crystallization (LIC). AIC of Hot Wire Chemical Vapour Deposited a-Si:H thin films was studied, to investigate the effect of different parameters, namely, layer sequence of deposition of a-Si:H and Al films, annealing temperature and time and thickness of layers, on the structural and electronic properties of resultant nc-Si films.
We have achieved device quality nc-Si thin films, at annealing temperatures ranging from 300°C to 400°C, which exhibits electronic properties favourable for piezoresistive MEMS sensor application. The nc-Si films obtained by AIC at an annealing temperature of 400°C showed hole concentration of the order of 1018 cm–3 and the hall mobility was measured to be approximately 20 cm2V–1sec–1. The films were subjected to piezoresistive gauge factor measurement and a gauge factor of 43 was recorded, which is highest reported till date for thin film nanocrystalline silicon.
Keywords: nanocrystalline, HWCVD, piezoresistive, MEMS, sensor