Session Mo-B2

TFT and Large Area Electronics II

Chair: Joon Seok Park, Samsung Advanced Institute of Technology

Mo-B2.1 16:00–16:20

Readout from Amorphous Silicon Thin-film Transistor-based Strain Sensing Sheets Over Non-contact Interfaces using a TFT Gilbert-Type Modulator

Warren Rieutort-Louis, Josue Sanz-Robinson, Yingzhe Hu, Liechao Huang, James C. Sturm, Naveen Verma, and Sigurd Wagner

Department of Electrical Engineering, Princeton University, Princeton, New Jersey, 08544, USA and the Princeton Institute for the Science and Technology of Materials (PRISM)

Large-area, thin-film, electronics (LAE) enables the development of electronic sheets with transformational capabilities and conformal form factors. Combining these with co-designed CMOS integrated circuits allows for leveraging of the computational power of CMOS in tandem with the rich sensing and energy-harvesting capabilities of LAE. Through the ability to incorporate amorphous silicon (a-Si) thin-film solar modules (PV), transistors (TFT), and sensors, as well as Li-Ion thin-film batteries, on flexible substrates, we have created complete, self-powered, sensing skin sheets [1,2]. For this system, TFT-based sensors [3] (e.g. for strain/light/pressure/chemical detection) are attractive from an integration-on-plastic perspective. Such sensors can be readily formed, and they exploit a rich set of physical responses, typically expressed through changes in TFT parameters such as mobility [4] or threshold voltage (Vt), resulting in TFT current shifts.

To enable the range of system components, patterning on different sheets, which are subsequently laminated, is preferred from a manufacturing perspective. To enable scalable system assembly, signal and power transfer between the sheets is performed wirelessly via non-contact interfaces using patterned planar capacitors/inductors; this enables large-scale systems without the need for costly and potentially low-reliability metallurgical bonding. Here, we demonstrate readout from a TFT strain sensor using a Gilbert-type modulator to achieve conversion of the sensor current output to an AC signal for transfer via a non-contact interface to a readout IC.

The Gilbert-type modulator consists firstly of a primary-TFT differential pair structure (T1/2), with thin-film n+ a-Si resistive loads (30 MΩ/sq); a TFT sensor serves as the tail current source (T3), biased in an appropriate regime for sensing mobility changes as a result of applied mechanical strain. The two inputs to the differential pair TFTs (T1/2) are counter-phase sinusoidal signals, which generate an amplified and AC-modulated output whose amplitude is proportional to the sensor-TFT (T3) current. This differential AC output can then be capacitively (wirelessly) coupled to an IC for readout; for efficient transfer, capacitive readout is used due to the limitation in operating frequency imposed by the low a-Si TFT ft of ~1MHz (as a result of low mobility and large parasitic capacitances). Such a structure, however, results in large AC amplitudes at the modulator output nodes, of which only a small fraction is representative of the actual strain-induced T3 current change. In addition, the intrinsic drain current drop due to TFT threshold voltage shift is also mirrored directly in this AC amplitude. To overcome these two issues, an additional TFT differential pair (T4/5) is used (also driven by sinusoidal inputs), whose outputs are connected to the outputs of the primary differential-pair structure, to cancel the sensor-independent signal. This additional differential pair uses an orthogonally laid-out strain-invariant reference TFT as its tail current source (T6). Assuming TFTs T6 and T3 are fairly well current-matched and experience similar Vt drift, the effect of this drift on the output AC signal of the TFTs is mitigated.

Using the described architecture, readout can be achieved from multiple TFT sensors by selectively gating each TFT sensor into the Gilbert-cell tail using a series of TFT access switches. In the complete system with a co-designed CMOS IC, non-contact TFT strain sensing on a cantilever-like structure is achieved up to 1000 microstrain (10−6 ΔL/L), with resolution of ~25 microstrain.

[1] Y. Hu, et al., VLSI Symposium, June 2013 (in press)

[2] W. Rieutort-Louis, et al., PVSC, June 2013 (in press)

[3] T. Someya, et al., MRS Bulletin, vol. 33, pp. 690–696, July 2008

[4] P. Servati, et al., Appl. Phys. Lett., vol. 86, 033504, Jan. 2005

Keywords: TFT circuit, sensor readout, electronic skin, flexible electronics, amorphous silicon

Mo-B2.2 16:20–16:40

Atomic Layer Deposited ZnO TFT with a Tunable Photoresponse in the Visible Regime

Ali K. Okyay (1,2), Feyza B. Oruç (2), and Levent E. Aygun (1)

1. Department of Electrical and Electronics Engineering, Bilkent University, Ankara 06800, Turkey

2. UNAM-Institute of Materials Science and Nanotechnology, Bilkent University, Ankara 06800, Turkey

ZnO grown at low temperature has crystallographic defects such as Zinc interstitials and Oxygen vacancies. Such crystal defects behave as electron donors yielding an effective n-type doping in ZnO. These defects also create trap states in the forbidden energy band that enable the emission and absorption of photons with energies lower than the band gap energy. However, there are no reports on the dynamic control of the density and occupancy of such trap states which would offer the ability to actively control electrical and optical properties of ZnO. In this work, we present a ZnO-channel TFT with actively tunable photoresponse to visible light using an external stimulus. The photocurrent is controlled by the application of a DC voltage bias at the gate terminal that modifies the local depletion layer profile in the metal-oxide-semiconductor (MOS) structure and the occupancy of deep level traps in the ZnO channel.

Photoluminescence (PL) measurement is performed on ZnO samples grown on quartz substrates. Room temperature PL characteristics of ZnO film at λ = 350 nm excitation exhibit luminescence in the 450–750 nm range, corresponding to below-bandgap emission, which reveals the presence of deep level traps within the forbidden band of ZnO. The energy distribution of the trap states in the forbidden band cause a broad emission centered around λ = 600 nm (2.07 eV). Two possible trap-assisted routes that would result in the emission of a photon with λ = 600 nm (2.07 eV) are discussed. The first scenario is the capture of a free electron from the conduction band by a trap state (unoccupied trap), and the second one is the recombination of an electron in a trap state (occupied trap) with a hole in the valence band. The latter predicts trap energy states are located in the forbidden band of ZnO, closer to the conduction band.

ZnO band edge is at 3.37 eV, however, lower energy photons can be absorbed through trap-assisted routes as described above. The magnitude of photocurrent generated by below-bandgap-photons depends on the density and availability of proper trap states. Therefore, the photogenerated current in the ZnO channel can be dynamically controlled via changing the occupancy of deep level traps by applied gate voltage bias. The gate voltage bias modifies the depletion region in the ZnO channel. When the channel is depleted, the deep level states are unoccupied, therefore strong absorption of sub-band gap photons is possible. In the accumulation mode, an accumulated region with a higher electron density and lower number of unoccupied states. Due to the decreasing number of empty trap states, the sub-bandgap photon absorption mechanism is suppressed. On the other hand, in the depletion mode applied gate bias repels electrons from the channel region and the quasi Fermi level is shifted down. Therefore, the probability of sub-bandgap photon absorption is boosted by the increase in the number of empty trap states.

Keywords: ZnO, visible light, photodetector, TFT, dynamic control, defects

Mo-B2.3 16:40–17:00

Comparative Study of PbS Thin Films Deposited from Modified Chemical Bath Solutions with Ammonia-Hidrazine and Ammonia-Hidrazine Free Precursors on TFTs Applications

Amanda Carrillo (1), Roberto Ambrosio (1), Abimael Jiménez (1), and Manuel Quevedo (2)

1. Instituto de Ingeniería y Tecnología, Universidad Autónoma de Ciudad Juárez. Ave del Charro 450 N Cd. Juárez Chih. CP 32310, México

2. Department of Materials Science and Engineering, University of Texas at Dallas, 800 West Campbell Rd., Richardson, TX 75083 USA

Amorphous silicon (a-Si:H) TFT is the most mature n-type TFT technology and is currently used in active matrix liquid crystal displays. While the a-Si:H TFT technology has emerged as the industry leader in applications such as active matrix liquid crystal display backplanes, its relatively low mobility (1cm2/Vs) and threshold voltage instability limits its use in applications that require significant device performance. Recents efforts to develop inorganic alternatives have lately involved the use of carbon nanotubes, graphene oxide, zinc oxide, etc. Inorganic binary II-VI chalcogenide thin film transistors are an attractive air-stable and high-mobility alternative to a-Si:H TFT technology and also for flexible electronics applications. One of the II-VI chalcogenides to attract recent attention for flexible electronics applications is lead sulfide (PbS). In particular, PbS thin films have been demonstrated using various chemical methods including chemical bath deposition (CBD), electrodeposition, successive ionic layer adsorption and reaction, spray pyrolysis, etc. Here we report the lead acetate/ sodium hydroxide/ triethanolamine/ thiourea system to grow the PbS active layers on glass substrates using the CBD method that we have reported before. After we performed a study comparative when we introduce the use of ammonia-hydrazine as complex agent in the CBD of PbS thin films and then we compared the two routes. Ammonia is one of the complexing agents which are the most commonly used in the precursors of PbS thin films by CBD and the hydrazine hydrate can be used as a reducing agent in the chemical bath to avoid the lead oxidation. PbS films were characterized through X-ray photoelectron spectroscopy (XPS), X-ray diffraction (XRD) and scanning electron microscopy (SEM) techniques to study thin film composition, structure and morphological characteristics respectively. The use of ammonia-hydrazine as complex agent in the CBD reduces the deposition rate due to high complexation and slow generation of Pb2+ improving the morphological characteristics. Less impurity on PbS films deposited at low deposition rate with the use of ammonia-hydrazine as complex agent were found through (XPS) measurments. X- ray diffraction studies showed the cubic crystalline phase of PbS. The two different PbS thin films deposition conditions were evaluated in TFTs. To do this PbS films with the best morphological and chemical characteristics were grown on hafnium oxide as material dielectric deposited by atomic layer deposition, this was grown on heavily doped Si wafers and we used source and drain gold contacts. The electrical characteristics of TFTs were determined using current-voltage (I-V) measurements at room temperature in a semiconductor characterization system. The best electrical performance was observed for films deposited at low deposition rates. These transistors, showed field effect mobility and threshold voltage of ~3x10–3 cm2/Vs and ~6 V, respectively. These characteristics in the PbS films make them a suitable candidate for various optoelectronic and device applications.

Keywords: chemical bath deposition; lead sulphide; thin films transistors

Mo-B2.6 (invited) 17:00–17:30 (new time)

Bias-Stress Effect in Dual Gate a-IGZO TFTs

M. Mallory and Jin Jang

Department of Information Display and Advanced Display Research Center, Kyung Hee University, Dongdaemoon-ku, Seoul 130-701, Korea

Dual gate TFTs have top and bottom gates with a-IGZO semiconductor and Mo source/drain electrodes. It is found that the threshold voltage can be controlled by sweeping the top gate potential or by bottom gate potential [1]. The effect of positive bias-stress to the bottom gate on the transfer curve depends on the offset length on the partially covered top gate in dual gate TFT structure such that mobility can be enhanced to >70 cm2/Vs and Vth shifts to the positive gate voltage [2]. The inverter performance can be improved by using the dual gate structure as driving or load TFT [1]. When bottom and top gates are connected together, the gate swing decreases and Vth shifts to zero voltage, indicting the improved device performance. The positive bias stress, negative bias stress and negative bias under illumination stress are also very different from those with single gate TFT. These results are also encouraging the use of dual gate TFTs for display applications. In this talk we will discuss the positive bias-stress, negative bias-stress and negative bias-stress under white light illumination in dual gate oxide TFTs.

[1] M. J. Seok, M. H. Choi, M. Mativenga, D. Geng, D. Y. Kim, and J. Jang, IEEE Electron Device Letters 32, 1089 (2011)

[2] M. Mallory, T. H. Hwang, J. Jang, APL Advances 2, 032129 (2012)

Mo-B2.4 17:00–17:20 Cancelled

Atomic Layer Deposited Titanium Dioxide as a Semiconductor for Thin Film Electronics

Feyza B. Oruç (2), Ali K. Okyay (1,2), and Furkan Cimen (1,2)

Mo-B2.5 17:20–17:40 Cancelled

Thin Film Transistors with Atomic Layer Deposited ZnO Grown at Different Temperatures

Feyza B. Oruç (2), Ali K. Okyay (1,2), Furkan Cimen (1,2)